publications

2025

1. SeaCache: Efficient and Adaptive Caching for Sparse Accelerators

   Xintong Li, Jinchen Jiang, and Mingyu Gao

   In Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture®, , 2025

   Abs DOI

   Sparse tensor computations are highly memory-bound, making on-chip data reuse in SRAM buffers critical to the performance of domain-specific sparse accelerators. On-demand caches are commonly used in recent sparse accelerators, due to the advantage of easy space allocation and the ability to avoid unnecessary data fetches compared to scratchpad-style data buffering. However, existing cache designs suffer from inefficient space utilization due to the difficulty of fitting variable-length sparse data into fixed-size cache blocks. The theoretically optimal replacement policies used by them also have substantial implementation cost, requiring significant on-chip space to manage the metadata. To address these issues, we propose SeaCache to enable efficient and adaptive caching for sparse accelerators. SeaCache includes three key techniques. First, it incorporates fiber packing and splitting to efficiently map variable-length data into fixed-size cache blocks with high space utilization. Second, it proposes a practical replacement policy that performs similarly to the optimal one but has a much cheaper implementation. Third, it shares the cache space between the actual data and the replacement policy metadata, with a two-phase adaptive mechanism to decide the best partition ratio. Overall, SeaCache outperforms state-of-the-art sparse cache designs by 2.8 \texttimes on average, demonstrating the effectiveness of its novel optimizations.

2. HYTE: Flexible Tiling for Sparse Accelerators via Hybrid Static-Dynamic Approaches

   Xintong Li, Zhiyao Li, and Mingyu Gao

   In Proceedings of the 52nd Annual International Symposium on Computer Architecture, , 2025

   Abs DOI

   Specialized hardware accelerators are widely used for sparse tensor computations. For very large tensors that do not fit in on-chip buffers, tiling is a promising solution to improve data reuse on these sparse accelerators. Nevertheless, existing tiling strategies on sparse accelerators are either purely dynamic and suffering from high design complexity, or purely static and using simple heuristics with insufficient adaptivity. In addition, they have not extensively explored the full design space of tiling to identify the optimal schemes, nor have they supported efficient management of the non-negligible metadata needed for tiling. We propose HYTE, a hybrid static-dynamic framework to enable flexible and efficient tiling on sparse accelerators. HYTE relies on a static offline scheduler to first identify a near-optimal initial tiling scheme through effective and lightweight sampling. The tile size and shape, the dimension iteration order across different tiles, and the buffer allocation policies can all be flexibly configured to adapt to the specific data sparsity patterns. Then at runtime, HYTE supports efficient management of the tiling metadata in both the off-chip memory and the on-chip buffer, as well as a technique of dynamic tuning on the tile shape to ensure high buffer utilization in the presence of highly varying local data patterns. Our evaluation shows that HYTE outperforms state-of-the-art sparse tiling strategies by 3.3 \texttimes to 6.2 \texttimes on average for diverse sparse matrices.

3. Adyna: Accelerating Dynamic Neural Networks with Adaptive Scheduling

   Zhiyao Li, Bohan Yang, Jiaxiang Li, and 3 more authors

   In 2025 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2025

   DOI

2020

1. Hardware-assisted service live migration in resource-limited edge computing systems

   Zhe Zhou, Xintong Li, Xiaoyang Wang, and 3 more authors

   In Proceedings of the 57th ACM/EDAC/IEEE Design Automation Conference, Virtual Event, USA, 2020

   Abs

   Service live migration means migrating the running services from one machine to another with negligible service downtime. It has been considered as a powerful mechanism to facilitate service management. However, conventional live migration methods always come with expensive cost of data transmission, and thus can hardly be applied to a real-world edge computing system directly due to the limited network bandwidth. To tackle this problem, some recent works present various techniques to reduce the data transmission.However, these techniques for data transmission reduction always introduce extra computational costs, which have a great impact on the quality of service (QoS), especially in edge systems containing lots of nodes with insufficient computational resources. To alleviate this issue, we propose an insight to offload data reduction computations to a specific hardware accelerator, thus reducing the burden of CPU cores. To this end, we present a novel hardware accelerator design to speed up the data transmission reduction computations to accelerate the service live migration. For evaluation, we implement a prototype on an FPGA platform. Compared to the normal CPU-based approaches, our specialized accelerator is 3.1\texttimes faster, 2.9\texttimes more-energy efficient, and can reduce 29% 47% of total migrating time and 24% 40% of service downtime in our cases. Furthermore, our architecture has great scalability and is easy-configurable to achieve a balance between cost and performance.